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AT88SC102 Card
AT88SC102 Card

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Features

• • • • • • • • • • • •

1K x 1 Serial E2PROM With Security Logic Available in Two Memory Organizations: AT88SC10111K x 1Memory Zone AT88SC1022512 x 1Memory Zone Supports ISO/IEC 7816-3 Synchronous Protocol Stores and Validates Security Codes Counts Incorrect Security Code Attempts Provides Transport Code Security Manufactured Using Low Power CMOS Technology VPP Internally Generated 2 µs Read Access Time; 5 ms Write Cycle Time Temperature Range From -25°C to 70°C ESD Immunity > 4K Volts High Reliability: 100,000 Write/Erase Cycles 100 Years Data Retention

Smart Card ICs 1K E2PROM with Security Logic AT88SC101 AT88SC102

Block Diagram

Description
The AT88SC101/102 family provides 1024 bits of serial E2PROM (Electrically Erasable and Programmable Read Only Memory) with additional security logic for use in secure smart card applications. The AT88SC101 is available in one 1024 x 1 bit memory zones, and the AT88SC102 is available in two 512 x 1 bit memory zones.

ISO Card Configuration
ISO Pad Pad Description Contact # Name
C1 C2 C3 C4 C5 C6 C7 C8 8 7 6 5 1 2 3 4 V CC RST CLK FUS VSS NC I/O PGM Operating Voltage Reset Clock and Address Control Identification Fuses Ground No Connect Bi-directional Data Port Programming Control

Card Module Contacts
Vcc RST

C1 C2 C3 C4

C5 C6 C7 C8

Vss N/C

CLK

I/O

FUS

PGM

The security features of Atmel’s AT88SC101/102 include: data access only after validation of the security code permanent invalidation of device upon four consecutive false security code presentations read/write protection of certain memory zones device reset if power drops

secure transport of devices using transport code compare sequence The AT88SC101/102 is manufactured using low-power CMOS technology and features its own internal high-voltage pump for single voltage supply operation. The devices are guaranteed to 100,000 erase/write cycles and 100 year data retention. Endurance up to one-million

AT88SC101 and AT88SC102 Memory Map
AT88SC101 Memory Partitions Fabrication Zone (FZ) Issuer Zone (IZ) Security Code (SC) Security Code Attempts Counter (SCAC) Code Protected Zone (CPZ) Application Zone 1 (AZ1) Application Zone 1 Erase Key (EZ1) Application Zone 2 (AZ2) Application Zone 2 Erase Key (EZ2) Erase Counter (EC) Memory Test Zone (MTZ) TOTAL BITS Address 0 - 15 16 - 79 80 - 95 96 - 111 112 - 175 176 - 1199 1200 - 1231 — — 1232 - 1359 1360 - 1375 Bits 16 64 16 16 64 1024 32 — — 128 16 1376 AT88SC102 Address 0 - 15 16 - 79 80 - 95 96 - 111 112 - 175 176 - 687 688 - 735 736 - 1247 1248 - 1279 1280 - 1407 1408 - 1423 Bits 16 64 16 16 64 512 48 512 32 128 16 1424

Definition of AT88SC101/102 Memory Partitions
FABRICATION ZONE (16 bits): Programmed by the manufacturer with a specific identifier for each customer. FUSE1 is blown by the manufacturer after programming the fabrication code, which makes the fabrication zone unalterable. ISSUER ZONE (64 bits): Programmed by the issuer before finalizing personalization. The data stored in the issuer zone is unalterable after FUSE2 is blown. SECURITY CODE (16 bits): Must be presented by the issuer to access circuit memory and personalize device before blowing FUSE2. This secures transportation between the manufacturer and the issuer. After the device is personalized and FUSE2 is blown, this code protects the access to the application zone(s) of the card. SECURITY CODE ATTEMPTS COUNTER (16 bits): Counts the number of incorrect security code attempts. The device is locked after 4 false presentations. USER PROTECTED ZONE (64 bits): Writing and erasing this zone is protected. The number of program/erase cycles is guaranteed up to 100,000. APPLICATION ZONE(S) (1024 or 512 bits): Reading and programming the application zone(s) are controlled by the first 2 bits of the zone (PR, RD) and by the security code (Tables 1 and 2). The erasure of each zone is protected by an erase key specific to each zone. APPLICATION ZONE ERASE KEY (32 or 48 bits): Must be presented to authorize the erasure of the application zone(s). The key(s) must be programmed during the personalization of the circuit. ERASE COUNTER (128 bits): Limits the number of erasures of the last zone to 128 or less. MEMORY TEST ZONE (16 bits): at this memory location. Allows pattern testing

2

AT88SC101/102

AT88SC101/102
Memory Access to AT88SC101 and AT88SC102
The access to the memory is controlled by the state of the internal fuses and by the voltage supply applied on the FUS pad: FUS Pad Voltage 0V 5V 5V State of the FUSES FUSE 1FUSE 2 Either Either Blown Not Blown Blown Blown Access Conditions See: Table 2 Table 1 Table 2

Table 1. AT88SC101/102 Access Conditions During Personalization (FUSE 2 Not Blown)
Zones

S C X 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 X

1 P R X X X X X X X X X X X X X X X X X X X X X X

1 R D X X X X X X X X X 0 1 X X X X X X X X X X X

2 P R X X X X X X X X X X X X X X X X X X X X X X

2 R D X X X X X X X X X X X X X X 0 1 X X X X X X

E Z 1 X X X X X X X X X X X X X X X X X X X X X X

E Z 2 X X X X X X X X X X X X X X X X X X X X X X

E C X X X X X X X X X X X X X X X X X X X X X X
2RD: EZ1: EZ2: EC:

READ

WRITE 1 (Erase) NO NO YES NO YES NO YES NO YES NO NO YES NO YES NO NO YES NO YES NO YES YES

WRITE 0 (PROG) NO NO YES NO YES YES YES NO YES NO NO YES NO YES NO NO YES NO YES YES YES YES

Compare

FZ IZ SC SCAC CPZ AZ1

YES YES YES NO YES YES YES YES YES NO YES YES NO YES NO YES YES NO YES YES YES YES

NO NO NO YES NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO NO

EZ1 AZ2

EZ2 EC MTZ
Notes:

SC:SC = 1 after validation of security code 1PR:1st bit of AZ1 (Bit 176) 1RD:2nd bit of AZ1(Bit 177) 2PR:1st bit of AZ2 (Bit 736) - AT88SC102 only

2nd bit of AZ2 (Bit 737) - AT88SC102 only EZ1 = 1 after a valid presentation of erase key 1 EZ2 = 1 after a valid presentation of erase key 2 EC = 1 when the counter is not empty.

3

Table 2. AT88SC101/102 Access Conditions After Personalization (FUSE 2 Blown)
Zones

S C X X 0 1 0 1 0 1 0 0 1 1 1 1 X 0 0 1 1 1 1 1 1 X X X

1 P R X X X X X X X X X X 0 0 1 1 X X X X X X X X X X X X

1 R D X X X X X X X X 0 1 X X X X X X X X X X X X X X X X

2 P R X X X X X X X X X X X X X X X X X 0 0 0 1 1 1 X X X

2 R D X X X X X X X X X X X X X X X 0 1 X X X X X X X X X

E Z 1 X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X

E Z 2 X X X X X X X X X X X X X X X X X 0 X 1 0 X 1 X X X

E C X X X X X X X X X X X X X X X X X X 0 1 X 0 1 X X X
2RD: EZ1: EZ2: EC:

READ

WRITE 1 (Erase) NO NO NO YES NO YES NO YES NO NO NO YES NO YES NO NO NO NO NO YES NO NO YES NO NO YES

WRITE 0 (PROG) NO NO NO YES YES YES NO YES NO NO NO NO YES YES NO NO NO NO NO NO YES YES YES NO YES YES

Compare

FZ IZ SC SCAC CPZ AZ1

YES YES NO NO YES YES YES YES NO YES YES YES YES YES NO NO YES YES YES YES YES YES YES NO YES YES

NO NO YES NO NO NO NO NO NO NO NO NO NO NO YES NO NO NO NO NO NO NO NO YES NO NO

EZ1 AZ2

EZ2 EC MTZ
Notes:

SC:SC = 1 after validation of security code 1PR:1st bit of AZ1 (Bit 176) 1RD:2nd bit of AZ1(Bit 177) 2PR:1st bit of AZ2 (Bit 736) - AT88SC102 only

2nd bit of AZ2 (Bit 737) - AT88SC102 only EZ1 = 1 after a valid presentation of erase key 1 EZ2 = 1 after a valid presentation of erase key 2 EC = 1 when the counter is not empty.

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AT88SC101/102

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